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preliminary data this is a preliminary information on a product now in developm ent or undergoing evaluation. details are subject to change witho ut notice. february 2006 rev 1 1/36 36 LIS3LV02DL mems inertial sensor 3-axis - 2g/ 6g digital output low volt age linear accelerometer features 2.16v to 3.6v single supply operation 1.8v compatible ios i 2 c/spi digital output interfaces programmable 12 or 16 bit data representation interrupt activated by motion programmable interrupt threshold embedded self test high shock survivability ecopack? comp liant (see section 8 ) description the LIS3LV02DL is a three axes digital output linear accelerometer that includes a sensing element and an ic interface able to take the information from the sensing element and to provide the measured acceleration signals to the external world through an i 2 c/spi serial interface. the sensing element, capable of detecting the acceleration, is manufactured using a dedicated process developed by st to produce inertial sensors and actuators in silicon. the ic interface instead is manufactured using a cmos process that allows high level of integration to design a dedicated circuit which is factory trimmed to better match the sensing element characteristics. the LIS3LV02DL has a user selectable full scale of 2g, 6g and it is capable of measuring acceleration over a bandwidth of 640 hz for all axes. the device bandwidth may be selected accordingly to the application requirements. a self-test capability allows the user to check the functioning of the system the device may be configured to generate an inertial wake-up/free-fall interrupt signal when a programmable acceleration threshold is crossed at least in one of the three axes. the LIS3LV02DL is available in plastic smd package and it is specified over a temperature range extending from -40c to +85c. the LIS3LV02DL belongs to a family of products suitable for a variety of applications: free-fall detection motion activated functions in portable terminals antitheft systems and inertial navigation gaming and virtual reality input devices vibration monitoring and compensation lga-16 order codes part number op. temp. range, cpackage packing LIS3LV02DL -40 to +85 lga-16 tray LIS3LV02DL-tr -40 to +85 lga-16 tape and reel www.st.com
contents LIS3LV02DL 2/36 contents 1 block diagram & pi n description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 lga-16 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 mechanical characteristics1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 electrical characteristics1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.4.1 sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.4.2 zero-g level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.4.3 self test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 sensing element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 ic interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3 factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1 soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1 i2c serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1.1 i2c operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2 spi bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2.1 spi read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2.2 spi write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2.3 spi read in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6 register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.1 who_am_i (0fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
LIS3LV02DL contents 3/36 7.2 offset_x (16h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.3 offset_y (17h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.4 offset_z (18h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.5 gain_x (19h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.6 gain_y (1ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.7 gain_z (1bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.8 ctrl_reg1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.9 ctrl_reg2 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.10 ctrl_reg3 (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.11 hp_filter_reset (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.12 status_reg (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.13 outx_l (28h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.14 outx_h (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.15 outy_l (2ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.16 outy_h (2bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.17 outz_l (2ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.18 outz_h (2dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.19 ff_wu_cfg (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.20 ff_wu_src (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.21 ff_wu_ack (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.22 ff_wu_ths_l (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.23 ff_wu_ths_h (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.24 ff_wu_duration (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.25 dd_cfg (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.26 dd_src (39h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.27 dd_ack (3ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.28 dd_thsi_l (3ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.29 dd_thsi_h (3dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.30 dd_thse_l (3eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.31 dd_thse_h (3fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
block diagram & pin description LIS3LV02DL 4/36 1 block diagram & pin description 1.1 block diagram figure 1. block diagram 1.2 lga-16 pin description figure 2. pin connection ? charge amplifier mux y+ z+ y- z- regs a x+ x- de mux reconstruction filter ? ? array i 2 c spi cs scl/spc sda/sdo/sdi sdo control logic & interrupt gen. rdy/int reconstruction filter reconstruction filter clock trimming circuits reference self test y 1 x z direction of the detectable accelerations LIS3LV02DL (top view) 1 6 7 8 9 14 15 16 cs scl/spc vdd_io sdo rdy/int gnd res vdd res vdd gnd nc ck gnd res sda/sdi/sdo
LIS3LV02DL block diagram & pin description 5/36 table 1. pin description pin# name function 1 rdy/int data ready/inertial wake-up interrupt 2 sdo spi serial data output 3 sda/ sdi/ sdo i 2 c serial data (sda) spi serial data input (sdi) 3-wire interface serial data output (sdo) 4 vdd_io power supply for i/o pads 5 scl/spc i 2 c serial clock (scl) spi serial port clock (spc) 6cs spi enable i 2 c/spi mode selection (1: i 2 c mode; 0: spi enabled) 7 nc internally not connected 8ck optional external clock, if not used either leave unconnected or connect to gnd 9 gnd 0v supply 10 reserved either leave uncon nected or connect to vdd_io 11 vdd power supply 12 reserved connect to vdd 13 vdd power supply 14 gnd 0v supply 15 reserved either leave unconnected or connect to gnd 16 gnd 0v supply
mechanical and electrical specifications LIS3LV02DL 6/36 2 mechanical and electrical specifications 2.1 mechanical characteristics 1 table 2. mechanical characteristics (all the parameters are specified @ vdd=3.3v, t=25c unless otherwise noted) symbol parameter tes t conditions min. typ. 2 max. unit fs measurement range 3 fs bit set to 0 1.7 2.0 g fs bit set to 1 5.3 6.0 g dres device resolution full-scale = 2g bw=40hz 1.0 mg so sensitivity full-scale = 2g, 12 bit representation 920 1024 1126 lsb/g full-scale = 6g, 12 bit representation 306 340 374 lsb/g tcs0 sensitivity change vs temperature full-scale = 2g, 12 bit representation 0.025 %/ c off zero-g level offset accuracy 4,5 full-scale = 2g x, y axis -70 70 mg full-scale = 2g z axis -90 90 mg full-scale = 6g x, y axis -90 90 mg full-scale = 6g z axis -100 100 mg lto f f zero-g level offset long term accuracy 6 full-scale = 2g x, y axis tbd %fs full-scale = 2g z axis tbd %fs full-scale = 6g x, y axis tbd %fs full-scale = 6g z axis tbd %fs tcoff zero-g level change vs temperature max delta from 25c 0.2 mg/ c
LIS3LV02DL mechanical and electr ical specifications 7/36 note: 1 the product is factory calibrated at 2.5v. the device can be used from 2.16v to 3.6v 2 typical specifications are not guaranteed 3 verified by wafer level test and measur ement of initial offset and sensitivity 4 zero-g level offset value after msl3 preconditioning 5 offset can be eliminated by enabling the built-in high pass filter (hpf) 6 results of accelerated reliability tests 7 self test output changes with the power supply. self test ?output change? is defined as output[lsb] (self-test bit on ctrl_reg1=1) -output[lsb] (self-test bit on ctrl_reg1=0) . 1lsb=1g/1024 at 12bit representation, 2g full-scale 8 output data reach 99% of final value after 5/odr when enabling self-test mode due to device filtering 9 odr is output data rate. refe r to table 3 for specifications nl non linearity best fit straight line x, y axis full-scale = 2g bw=40hz 2%fs best fit straight line z axis full-scale = 2g bw=40hz 3 %fs crax cross axis -3.5 3.5 % v st self test output change 7,8 full-scale=2g x axis 250 550 900 lsb full-scale=2g y axis 250 550 900 lsb full-scale=2g z axis -100 -350 -600 lsb full-scale=6g x axis 80 180 300 lsb full-scale=6g y axis 80 180 300 lsb full-scale=6g z axis -30 -120 -200 lsb bw system bandwidth 9 odrx/4 hz to p operating temperature range -40 +85 c wh product weight 72 mgram table 2. mechanical characteristics (continued) (all the parameters are specified @ vdd=3.3v, t=25c unless otherwise noted) symbol parameter tes t conditions min. typ. 2 max. unit
mechanical and electrical specifications LIS3LV02DL 8/36 2.2 electrical characteristics 1 note: 1 the product is factory calibrated at 2.5v. the device can be used from 2.16v to 3.6v 2 typical specifications are not guaranteed 3 digital filter cut-off frequency 4 time to obtain valid data after exiting power-down mode table 3. electrical characteristics (all the parameters are specified @ vdd=2.5v, t=25c unless otherwise noted) symbol parameter tes t conditions min. typ. 2 max. unit vdd supply voltage 2.16 2.5 3.6 v vdd_io i/o pads supply voltage 1.71 vdd v idd supply current t = 25c, vdd=3.3v 0.65 0.80 ma vih digital high level input voltage 0.8*vdd _io v vil digital low level input voltage 0.2*vdd _io v voh high level output voltage 0.9*vdd _io v vol low level output voltage 0.1*vdd _io v iddpdn current consumption in power-down mode t = 25c 1 10 a odr1 output data rate1 dec factor = 512 40 hz odr2 output data rate 2 dec factor = 128 160 hz odr3 output data rate 3 dec factor = 32 640 hz odr4 output data rate 4 dec factor = 8 2560 hz bw system bandwidth 3 odrx/4 hz to n turn-on time 4 5/odrx s fmax spi frequency vdd_io<2.4v 4 mhz vdd_io>2.4v 8 mhz to p operating temperature range -40 +85 c
LIS3LV02DL mechanical and electr ical specifications 9/36 2.3 absolute maximum ratings stresses above those listed as ?absolute maxi mum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. table 4. absolute maximum ratings note: 1 supply voltage on any pin should never exceed 6.0v. symbol ratings maximum value unit vdd supply voltage -0.3 to 6 v vdd_io i/o pins supply voltage -0.3 to vdd +0.1 v vin input voltage on any control pin (cs, scl/spc, sda/sdi/sdo, ck) -0.3 to vdd_io +0.3 v a pow acceleration (any axis, powered, vdd=2.5v) 3000g for 0.5 ms 10000g for 0.1 ms a unp acceleration (any axis, unpowered) 3000g for 0.5 ms 10000g for 0.1 ms t op operating temperature range -40 to +85 c t stg storage temperature range -40 to +125 c esd electrostatic discharge protection 4.0 (hbm) kv 200 (mm) v 1.5 (cdm) kv this is a mechanical shock sensitive device, improper handling can cause permanent damages to the part this is an esd sensitive device, improper handling can cause permanent damages to the part
mechanical and electrical specifications LIS3LV02DL 10/36 2.4 terminology 2.4.1 sensitivity sensitivity describes the gain of the sensor and can be determined e.g. by applying 1g acceleration to it. as the sensor can measure dc accelerations this can be done easily by pointing the axis of interest towards the center of the earth, noting the output value, rotating the sensor by 180 degrees (point to the sky) an d noting the output value again. by doing so, 1g acceleration is applied to the sensor. subtracting the larger output value from the smaller one and divide the result by 2 leads to the actual sensitivity of the sensor. this value changes very little over temperature and also very little over time. the sensitivity tolerance describes the range of sensitivities of a large population of sensor. 2.4.2 zero-g level zero-g level offset (off) describes the deviation of an actual output signal from the ideal output signal if there is no accelerati on present. a sensor in a steady state on a horizontal surface will measure 0g in x axis and 0g in y axis whereas the z axis will measure 1g . the output is ideally in the middle of the dynamic range of the sensor (content of out registers 00h, 00h with 16 bit representation, data expressed as 2?s complement number). a deviation from ideal value in this case is called zero-g offset. offset is to some extent a result of stress to a precise mems sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. offset changes little over temperature, see ?zero-g level change vs. temperature?. the zero-g level of an individual sensor is stable over lifetime. the zero-g level tolerance describes the range of zero-g levels of a population of sensors. 2.4.3 self test self test allows to test the mechanical and electric part of the sensor, allowing the seismic mass to be moved by means of an electrostatic test-force. the self test function is off when the self-test bit of ctrl_reg1 (control register 1) is programmed to ?0?. when the self-test bit of ctrl_reg1 is programmed to ?1? an actuation forc e is applied to the sensor, simulating a definite input acceleration. in this case the sensor outputs will exhibit a ch ange in their dc levels which is related to the selected full scale and depending on the supply voltage through the device sensitivity. when self test is activated, the device output level is given by the algebraic sum of the signals produced by the acceleration acting on the sensor and by the electrostatic test- force. if the output signals change within the amplitude specified inside table 2 than the sensor is working properly and the parameters of the in terface chip are within the defined specification.
LIS3LV02DL functionality 11/36 3 functionality the LIS3LV02DL is a high performance, low-power, digital output 3-axis linear accelerometer packaged in a lga package. the complete device includes a sensing element and an ic interface able to take the information from the sensing element and to provide a signal to the external world through an i 2 c/spi serial interface. 3.1 sensing element a proprietary process is used to create a surface micro-machined accelerometer. the technology allows to carry out suspended silicon st ructures which are atta ched to the substrate in a few points called anchors and are free to move in the direction of the sensed acceleration. to be compatible with the traditional packaging techniques a cap is placed on top of the sensing element to avoid blocking the moving parts during the moulding phase of the plastic encapsulation. when an acceleration is applied to the sensor the proof mass displaces from its nominal position, causing an imbalance in the capacitive half-bridge. this imbalance is measured using charge integration in response to a voltage pulse applied to the sense capacitor. at steady state the nominal value of the capacitors are few pf and when an acceleration is applied the maximum variation of the capacitive load is up to 100ff. 3.2 ic interface the complete measurement chain is composed by a low-noise capacitive amplifier which converts into an analog voltage the capacitive unbalancing of the mems sensor and by three ? analog-to-digital converters, one for each axis, that translate the produced signal into a digital bitstream. the ? converters are coupled with dedicated reconstruction filters which remove the high frequency components of the quantization noise and provide low rate and high resolution digital words. the charge amplifier and the ? converters are operated respectively at 61.5 khz and 20.5 khz. the data rate at the output of the reconstruction depends on the user selected decimation factor (df) and spans from 40 hz to 2560 hz. the acceleration data may be accessed through an i 2 c/spi interface thus making the device particularly suitable for direct interfacing with a microcontroller. the LIS3LV02DL features a data-ready signal (rdy) which indicates when a new set of measured acceleration data is available thus simplifying data synchronization in digital system employing the device itself. the LIS3LV02DL may also be configured to generate an inertial wake-up, direction detection and free-fall interrupt signal accordingly to a programmed acceleration event along the enabled axes.
functionality LIS3LV02DL 12/36 3.3 factory calibration the ic interface is factory calibrated for sensitivity (so) and zero-g level (off). the trimming values are stored inside the device by a non volatile structure. any time the device is turned on, the trimming parameters are downloaded into the registers to be employed during the normal operation. this allows the user to employ the device without further calibration.
LIS3LV02DL application hints 13/36 4 application hints figure 3. LIS3LV02DL electrical connection the device core is supplied through vdd line while the i/o pads are supplied through vdd_io line. power supply decoupling capacitors (100 nf ceramic, 10 f al) should be placed as near as possible to the pin 13 of the device (common design practice). all the voltage and ground supplies must be present at the same time to have proper behavior of the ic (refer to fig. 3). it is possible to remove vdd mantaining vdd_io without blocking the communication busses. the functionality of the device and the measured acceleration data is selectable and accessible through the i 2 c/spi interface.when using the i 2 c, cs must be tied high while sdo must be left floating. refer to dedicated application note for further information on device usage. 4.1 soldering information the lga-16 package is lead free and green package qualified for soldering heat resistance according to jedec j-std-020c. pin #1 indicato r are physically connected to gnd. soldering recommendations are available upon request. direction of the detectable accelerations vdd_io cs scl/spc sda/sdi/sdo sdo rdy/int 10uf vdd digital signal from/to signal controller.signal?s levels are defined by proper selection of vdd_io 100nf gnd LIS3LV02DL (top view) 1 6 7 8 9 14 15 16 y 1 x z
digital interfaces LIS3LV02DL 14/36 5 digital interfaces the registers embedded inside the LIS3LV02DL may be accessed through both the i 2 c and spi serial interfaces. the latter may be sw configured to operate either in 3-wire or 4-wire interface mode. the serial interfaces are mapped onto the same pads. to select/exploit the i 2 c interface, cs line must be tied high (i.e connected to vdd_io). table 5. serial interface pin description 5.1 i 2 c serial interface the LIS3LV02DL i 2 c is a bus slave. the i 2 c is employed to write the data into the registers whose content can also be read back. the relevant i 2 c terminology is given in the table below table 6. serial interface pin description there are two signals associated with the i 2 c bus: the serial clock line (scl) and the serial data line (sda). the latter is a bidirectional line used for sending and receiving the data to/from the interface. both the lines are connected to vdd_io through a pull-up resistor embedded inside the LIS3LV02DL. when the bus is free both the lines are high. the i 2 c interface is comp liant with fast mode (400 khz) i 2 c standards as well as the normal mode. pin name pin description cs spi enable i 2 c/spi mode selection (1: i 2 c mode; 0: spi enabled) scl/spc i 2 c serial clock (scl) spi serial port clock (spc) sda/sdi/sdo i 2 c serial data (sda) spi serial data input (sdi) 3-wire interface serial data output (sdo) sdo spi serial data output (sdo) term description transmitter the device which sends data to the bus receiver the device which receives data from the bus master the device which initiates a transfer, generates clock signals and terminates a transfer slave the device addressed by the master
LIS3LV02DL digital interfaces 15/36 5.1.1 i 2 c operation the transaction on the bus is started through a start (st) signal. a start condition is defined as a high to low transition on the data line while the scl line is held high. after this has been transmitted by the master, the bus is considered busy. the next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the slave. when an address is sent, each device in the system compares the first seven bits after a start condition with its address. if they match, the device considers itself addressed by the master. the slave address (sad) associated to the LIS3LV02DL is 0011101b. data transfer with acknowledge is mandatory. the transmitter must release the sda line during the acknowledge pulse. the receiver must then pull the data line low so that it remains stable low during the high period of the acknowledge clock pulse. a receiver which has been addressed is obliged to generate an acknowledge after each byte of data has been received. the i 2 c embedded inside the LIS3LV02DL behaves like a slave device and the following protocol must be adhered to. after the start condition (st) a salve address is sent, once a slave acknowledge (sak) has been re turned, a 8-bit sub-address will be transmitted: the 7 lsb represent the actual register address while the msb enables address auto increment. if the msb of the sub field is 1, the sub (register address) will be automatically incremented to allow multiple data read/write. the slave address is completed with a read/write bit. if the bit was ?1? (read), a repeated start (sr) condition will have to be issued after the two sub-address bytes; if the bit is ?0? (write) the master will tran smit to the slave with direction unchanged. transfer when master is writing one byte to slave transfer when master is writ ing multiple bytes to slave: transfer when master is receiving (reading) one byte of data from slave: transfer when master is receiving (reading) multiple bytes of data from slave data are transmitted in byte format (data). each data transfer contains 8 bits. the number of bytes transferred per transfer is unlimited. data is transferred with the most significant bit (msb) first. if a receiver can?t receive another complete byte of data until it has performed some other master st sad + w sub data sp slave sak sak sak master st sad + w sub data data sp slave sak sak sak sak master st sad + w sub sr sad + r nmak sp slave sak sak sak data master st sad + w sub sr sad + r mak slave sak sak sak data master mak nmak sp s l a ve data data
digital interfaces LIS3LV02DL 16/36 function, it can hold the clock line, scl low to force the transmitter into a wait state. data transfer only continues when the receiver is ready for another byte and releases the data line. if a slave receiver doesn?t acknowledge the slave address (i.e. it is not able to receive because it is performing some real time function) the data line must be left high by the slave. the master can then abort the transfer. a low to high transition on the sda line while the scl line is high is defined as a stop condition. each data transfer must be terminated by the generation of a stop (sp) condition. in order to read multiple bytes, it is necessary to assert the most significant bit of the sub- address field. in other words, sub(7) must be equal to 1 while sub(6-0) represents the address of first register to read. in the presented communication format mak is master acknowledge and nmak is no master acknowledge. 5.2 spi bus interface the LIS3LV02DL spi is a bus slave. the spi allows to write and read the registers of the device. the serial interface interacts with the outside world with 4 wires: cs , spc , sdi and sdo . figure 4. read & write protocol cs is the serial port enable and it is controlled by the spi master. it goes low at the start of the transmission and goes back high at the end. spc is the serial port clock and it is controlled by the spi master. it is stopped high when cs is high (no transmission). sdi and sdo are respectively the serial port da ta input and output. th ose lines are driven at the falling edge of spc and should be captured at the rising edge of spc . both the read register and write register commands are completed in 16 clock pulses or in multiple of 8 in case of multiple byte read/write. bit duration is the time between two falling edges of spc . the first bit (bit 0) starts at the first falling edge of spc after the falling edge of cs while the last bit (bit 15, bit 23 , ...) starts at the last falling ed ge of spc just before the rising edge of cs . bit 0 : rw bit. when 0, the data di(7:0) is written into the device. when 1, the data do(7:0) from the device is read. in latter case, the chip will drive sdo at the start of bit 8. bit 1 : ms bit. when 0, the address will remain unchanged in mult iple read/write commands. when 1, the address will be auto incremented in mult iple read/write commands. bit 2-7 : address ad(5:0). this is the address field of the indexed register. cs spc sdi sdo rw ad5 ad4 ad3 ad2 ad1 ad0 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 ms
LIS3LV02DL digital interfaces 17/36 bit 8-15 : data di(7:0) (write mode). this is the dat a that will be written in to the device (msb first). bit 8-15 : data do(7:0) (read mode). this is the data that will be read from the device (msb first). in multiple read/write comm ands further blocks of 8 cloc k periods will be added. when ms bit is 0 the address used to read/write data remains the same for every block. when ms bit is 1 the address used to read/write data is incremented at every block. the function and the behavior of sdi and sdo remain unchanged. 5.2.1 spi read figure 5. spi read protocol the spi read command is performed with 16 clock pulses. multiple byte read command is performed adding blocks of 8 clock pulses at the previous one. bit 0 : read bit. the value is 1. bit 1 : ms bit. when 0 do not increment address, when 1 increment address in multiple reading. bit 2-7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data do(7:0) (read mode). this is the data that will be read from the device (msb first). bit 16-... : data do(...-8). further data in multiple byte reading. figure 6. multiple bytes spi read protocol (2 bytes example) cs spc sdi sdo rw do7 do6 do5 do4 do3 do2 do1 do0 ad5 ad4 ad3 ad2 ad1 ad0 ms cs spc sdi sdo rw do7 do6 do5 do4 do3 do2 do1 do0 ad5 ad4 ad3 ad2 ad1 ad0 do15 do14 do13 do12 do11 do10 do9 do8 ms
digital interfaces LIS3LV02DL 18/36 5.2.2 spi write figure 7. spi write protocol the spi write command is performed with 16 clock pulses. multiple byte write command is performed adding blocks of 8 clock pulses at the previous one. bit 0 : write bit. the value is 0. bit 1 : ms bit. when 0 do not increment address, when 1 increment address in multiple writing. bit 2 -7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data di(7:0) (write mode). this is the dat a that will be written in side the device (msb first). bit 16-... : data di(...-8). further data in multiple byte writing. figure 8. multiple bytes spi write protocol (2 bytes example) 5.2.3 spi read in 3-wires mode 3-wires mode is entered by setting to 1 bit sim (spi serial interface mode selection) in ctrl_reg2. figure 9. spi read protocol in 3-wires mode cs spc sdi rw di7 di6 di5 di4 di3 di2 di1 di0 ad5 ad4 ad3 ad2 ad1 ad0 ms cs spc sdi rw ad5 ad4 ad3 ad2 ad1 ad0 di7 di6 di5 di4 di3 di2 di1 di0 di15 di 14 di13 di12 di11 di10 di9 di8 ms cs spc sdi/o rw do7 do6 do5 do4 do3 do2 do1 do0 ad5 ad4 ad3 ad2 ad1 ad0 ms
LIS3LV02DL digital interfaces 19/36 the spi read command is performed with 16 clock pulses: bit 0 : read bit. the value is 1. bit 1 : ms bit. when 0 do not increment address, when 1 increment address in multiple reading. bit 2-7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data do(7:0) (read mode). this is the data that will be read from the device (msb first). multiple read command is also available in 3-wires mode.
register mapping LIS3LV02DL 20/36 6 register mapping the table given below provides a listing of the 8 bit registers embedded in the device and the related address. table 7. registers address map reg. name type register address default comment binary hex rw 0000000 - 0001110 00 - 0e reserved who_am_i r 0001111 0f 00111010 dummy register rw 0010000 - 0010101 10-15 reserved offset_x rw 0010110 16 calibration loaded at boot offset_y rw 0010111 17 calibration loaded at boot offset_z rw 0011000 18 calibration loaded at boot gain_x rw 0011001 19 calibration loaded at boot gain_y rw 0011010 1a calibration loaded at boot gain_z rw 0011011 1b calibration loaded at boot 0011100 -0011111 1c-1f reserved ctrl_reg1 rw 0100000 20 00000111 ctrl_reg2 rw 0100001 21 00000000 ctrl_reg3 rw 0100010 22 00001000 hp_filter reset r 0100011 23 dummy dummy register 0100100-0100110 24-26 not used status_reg rw 0100111 27 00000000 outx_l r 0101000 28 output outx_h r 0101001 29 output outy_l r 0101010 2a output outy_h r 0101011 2b output outz_l r 0101100 2c output outz_h r 0101101 2d output r 0101110 2e reserved 0101111 2f not used ff_wu_cfg rw 0110000 30 00000000 ff_wu_src rw 0110001 31 00000000 ff_wu_ack r 0110010 32 dummy dummy register 0110011 33 not used ff_wu_ths_l rw 0110100 34 00000000
LIS3LV02DL register mapping 21/36 registers marked as reserved must not be changed. the writing to those registers may cause permanent damages to the device. the content of the registers that are loaded at boot should not be changed. they contain the factory calibration values. their content is automatically restored when the device is powered- up. ff_wu_ths_h rw 0110101 35 00000000 ff_wu_duration rw 0110110 36 00000000 0110111 37 not used dd_cfg rw 0111000 38 00000000 dd_src rw 0111001 39 00000000 dd_ack r 0111010 3a dummy dummy register 0111011 3b not used dd_thsi_l rw 0111100 3c 00000000 dd_thsi_h rw 0111101 3d 00000000 dd_thse_l rw 0111110 3e 00000000 dd_thse_h rw 0111111 3f 00000000 1000000-1111111 40-7f reserved table 7. registers address map (continued) reg. name type register address default comment binary hex
register description LIS3LV02DL 22/36 7 register description the device contains a set of registers which are used to control its behavior and to retrieve acceleration data. the registers 7.2 to 7.7 contain the factory calibration values, it is not necessary to change their value for normal device operation. 7.1 who_am_i (0fh) addressing this register the ph ysical address of the device is returned. for LIS3LV02DL the physical address assigned in factory is 3ah. 7.2 offset_x (16h) 7.3 offset_y (17h) 7.4 offset_z (18h) w7 w6 w5 w4 w3 w2 w1 w0 w7, w0 LIS3LV02DL physical address equal to 3ah ox7 ox6 ox5 ox4 ox3 ox2 ox1 ox0 ox7, ox0 digital offset trimming for x-axis oy7 oy6 oy5 oy4 oy3 oy2 oy1 oy0 oy7, oy0 digital offset trimming for y-axis oz7oz6oz5oz4oz3oz2oz1oz0 oz7, oz0 digital offset trimming for z-axis
LIS3LV02DL register description 23/36 7.5 gain_x (19h) 7.6 gain_y (1ah) 7.7 gain_z (1bh) 7.8 ctrl_reg1 (20h) pd1, pd0 bit allows to turn on the turn the device out of power-down mode. the device is in power-down mode when pd1, pd0= ?00? (default value after boot). the device is in normal mode when either pd1 or pd0 is set to 1. df1, df0 bit allows to select the data rate at which acceleration samples are produced. the default value is 00 which corresponds to a data-ra te of 40hz. by changing the content of df1, df0 to ?01?, ?10? and ?11? the selected data-rate will be set respec tively equal to 160hz, 640hz and to 2560hz. gx7 gx6 gx5 gx4 gx3 gx2 gx1 gx0 gx7, gx0 digital gain trimming for x-axis gy7gy6gy5gy4gy3gy2gy1gy0 gy7, gy0 digital gain trimming for y-axis gz7gz6gz5gz4gz3gz2gz1gz0 gz7, gz0 digital gain trimming for z-axis pd1 pd0 df1 df0 st zen yen xen pd1, pd0 power down control (00: power-down mode; 01, 10, 11: device on) df1, df0 decimation factor control (00: decimate by 512; 01: decimate by 128; 10: decimate by 32; 11: decimate by 8) st self test enable (0: normal mode; 1: self-test active) zen z-axis enable (0: axis off; 1: axis on) ye n y-axis enable (0: axis off; 1: axis on) xen x-axis enable (0: axis off; 1: axis on)
register description LIS3LV02DL 24/36 st bit is used to activate the se lf test function. when the bit is set to one, an output change will occur to the device outputs (refer to table 2 an d 3 for specification) thus allowing to check the functionality of the whole measurement chain. zen bit enables the z-axis measurement channel when set to 1. the default value is 1. yen bit enables the y-axis measurement channel when set to 1. the default value is 1. xen bit enables the x-axis measurement channel when set to 1. the default value is 1. 7.9 ctrl_reg2 (21h) fs bit is used to select full scale value. after the device power-up the default full scale value is +/-2g. in order to obtain a +/-6g full scale it is necessary to set fs bit to ?1?. bdu bit is used to inhibit output registers update until both upper and lower register parts are read. in default mode (bdu= ?0?) the output register values are updated continuously. if for any reason it is not sure to read faster than output data rate it is recommended to set bdu bit to ?1?. in this way the content of output registers is not updated until both msb and lsb are read avoiding to read values related to different sample time. ble bit is used to select big endian or little endi an representation for output registers. in big endian?s one msb acceleration value is located at addresses 28h (x-axis), 2ah (y-axis) and 2ch (z-axis) while lsb acceleration value is located at addresses 29h (x-axis), 2bh (y-axis) and 2dh (z-axis). in little endian representation (default, ble=?0?) the order is inverted (refer to data register description for more details). boot bit is used to refresh the content of internal registers stored in the flash memory block. at the device power up the content of the flash memory block is transferred to the internal registers related to trimming functions to permit a good behavior of the device itself. if for any reason the content of trimming registers was changed it is sufficient to use this bit to restore correct values. when boot bit is set to ?1? the content of internal flash is copied inside corresponding internal registers and it is used to calibrate the device. these values are factory fs bdu ble boot ien drdy sim das fs full scale selection (0: 2g; 1: 6g) bdu block data update (0: continuous update; 1: output regist ers not updated until msb and lsb reading) ble big/little endian selection (0: little endian; 1: big endian) boot reboot memory content ien interrupt enable (0: data ready on rdy pad; 1: int req on rdy pad) drdy enable data-ready generation sim spi serial interface mode selection (0: 4-wire interface; 1: 3-wire interface) das data alignment selection (0: 12 bit right justified; 1: 16 bit left justified)
LIS3LV02DL register description 25/36 trimmed and they are different for every accelerometer. they permit a good behavior of the device and normally they have not to be changed. at the end of the boot process the boot bit is set again to ?0?. ien bit is used to switch the value present on data-ready pad between data-ready signal and interrupt signal. at power up the data-ready signal is chosen. it is however necessary to modify drdy bit to enable data-ready signal generation. drdy bit is used to enable data-ready (rdy/int) pin activation. if drdy bit is ?0? (default value) on data-ready pad a ?0? value is present. if a data-ready signal is desired it is necessary to set to ?1? drdy bit. data-ready signal goes to ?1? whenever a new data is available for all the enabled axis. for example if z-axis is disabled, data -ready signal goes to ?1? when new values are available for both x and y axis. data-ready signal comes back to ?0? when all the registers containing values of the enabled axis are read. to be sure not to loose any data coming from the accelerometer data registers must be read before a new data-ready rising edge is generated. in this case data-read y signal will have the same frequency of the data rate chosen. sim bit selects the spi serial interface mode. when sim is ?0? (default value) the 4-wire interface mode is selected. the data coming from the device are sent to sdo pad. in 3-wire interface mode output data are sent to sda_sdi pad. das bit permits to decide between 12 bit right justified and 16 bit left justified representation of data coming from the device. the first case is the default case and the most significant bits are replaced by the bit representing the sign. 7.10 ctrl_reg3 (22h) fds bit enables (fds=1) or bypass (fds=0) the high pass filter in the signal chain of the sensor cfs1, cfs0 bits defines the coefficient hpc to be used to calculate the -3db cut-off frequency of the high pass filter: eck hpdd hpff fds res res cfs1 cfs0 eck external clock. default value: 0 (0: clock from internal oscillator; 1: clock from external pad) hpdd high pass filter enabled for direction detection. default value: 0 (0: filter bypassed; 1: filter enabled) hpff high pass filter enabled for free-fall and wake-up. default value: 0 (0: filter bypassed; 1: filter enabled) fds filtered data selection. default value: 0 (0: internal filter bypassed; 1: data from internal filter) cfs1, cfs0 high-pass filter cut-off frequency selection. default value: 00 (00: hpc=512 01: hpc=1024 10: hpc=2048 11: hpc=4096) f cutoff 0.318 hpc ------------- odrx 2 ---------------- ? =
register description LIS3LV02DL 26/36 7.11 hp_filter_reset (23h) dummy register. reading at this address zeroes instantaneously the content of the internal high pass-filter. read data is not significant. 7.12 status_reg (27h) 7.13 outx_l (28h) in big endian mode (bit ble ctrl_reg2 set to ?1?) the content of this register is the msb acceleration data and depends by bit das in ctr_reg2 reg as described in the following section. 7.14 outx_h (29h) when reading the register in ?12 bit right justified? mode the most significant bits (15:12) are replaced with bit 11 (i.e. xd15-xd12=xd11, xd11, xd11, xd11). in big endian mode (bit ble ctrl_reg2 set to ?1?) the content of this register is the lsb acceleration data. zyxor zor yor xor zyxda zda yda xda zyxor x, y and z axis data overrun zor z axis data overrun yor y axis data overrun xor x axis data overrun zyxda x, y and z axis new data available zda z axis new data available yda y axis new data available xda x axis new data available xd7 xd6 xd5 xd4 xd3 xd2 xd1 xd0 xd7, xd0 x axis acceleration data lsb xd15 xd14 xd13 xd12 xd11 xd10 xd9 xd8 xd15, xd8 x axis acceleration data msb
LIS3LV02DL register description 27/36 7.15 outy_l (2ah) in big endian mode (bit ble ctrl_reg2 set to ?1?) the content of this register is the msb acceleration data and depends by bit das in ctr_reg2 reg as described in the following section. 7.16 outy_h (2bh) when reading the register in ?12 bit right justified? mode the most significant bits (15:12) are replaced with bit 11 (i.e. yd15-yd12=yd11, yd11, yd11, yd11). in big endian mode (bit ble ctrl_reg2 set to ?1?) the content of this register is the lsb acceleration data. 7.17 outz_l (2ch) in big endian mode (bit ble ctrl_reg2 set to ?1?) the content of this register is the msb acceleration data and depends by bit das in ctr_reg2 reg as described in the following section. 7.18 outz_h (2dh) when reading the register in ?12 bit right justified? mode the most significant bits (15:12) are replaced with bit 11 (i.e. zd15-zd12=zd11, zd11, zd11, zd11). in big endian mode (bit ble ctrl_reg2 set to ?1?) the content of this register is the lsb acceleration data yd7 yd6 yd5 yd4 yd3 yd2 yd1 yd0 yd7, yd0 y axis acceleration data lsb yd15 yd14 yd13 yd12 yd11 yd10 yd9 yd8 yd15, yd8 y axis acceleration data msb zd7 zd6 zd5 zd4 zd3 zd2 zd1 zd0 zd7, zd0 z axis acceleration data lsb zd15 zd14 zd13 zd12 zd11 zd10 zd9 zd8 zd15, zd8 z axis acceleration data msb
register description LIS3LV02DL 28/36 7.19 ff_wu_cfg (30h) free-fall and inertial wake-up configuration register. aoi lir zhie zlie yhie ylie xhie xlie aoi and/or combination of interrupt events interrupt request. default value: 0. (0: or combination of interrupt events; 1: and combination of interrupt events) lir latch interrupt request. default value: 0. (0: interrupt request not latched; 1: interrupt request latched) zhie enable interrupt request on z high event. default value: 0. (0: disable interrupt request; 1: enable interrupt request on measured acce l. value higher than preset threshold) zlie enable interrupt request on z low event. default value: 0. (0: disable interrupt request; 1: enable interrupt request on measured acce l. value lower than preset threshold) yhie enable interrupt request on y high event. default value: 0. (0: disable interrupt request; 1: enable interrupt request on measured acce l. value higher than preset threshold) ylie enable interrupt request on y low event. default value: 0. (0: disable interrupt request; 1: enable interrupt request on measured acce l. value lower than preset threshold) xhie enable interrupt request on x high event. default value: 0. (0: disable interrupt request; 1: enable interrupt request on measured acce l. value higher than preset threshold) xlie enable interrupt request on x low event. default value: 0. (0: disable interrupt request; 1: enable interrupt request on measured acce l. value lower than preset threshold)
LIS3LV02DL register description 29/36 7.20 ff_wu_src (31h) 7.21 ff_wu_ack (32h) dummy register. if lir bit in ff_wu_cfg=1 allows the refresh of ff_wu_src. read data is not significant. x ia zhzlyhylxhxl ia interrupt active. default value: 0 (0: no interrupt has been generated; 1: one or more interrupt event has been generated) zh z high. default value: 0 (0: no interrupt; 1: zh event has occurred) zl z low. default value: 0 (0: no interrupt; 1: zl event has occurred) yh y high. default value: 0 (0: no interrupt; 1: yh event has occurred) yl y low. default value: 0 (0: no interrupt; 1: yl event has occurred) xh x high. default value: 0 (0: no interrupt; 1: xh event has occurred) xl x low. default value: 0 (0: no interrupt; 1: xl event has occurred)
register description LIS3LV02DL 30/36 7.22 ff_wu_ths_l (34h) 7.23 ff_wu_ths_h (35h) 7.24 ff_wu_duration (36h) set the minimum duration of the free-fall/wake-up event to be recognized. ths7 ths6 ths5 ths4 ths3 ths2 ths1 ths0 ths7, ths0 free-fall / inertial wake up acceleration threshold lsb ths15 ths14 ths13 ths12 ths11 ths10 ths9 ths8 ths15, ths8 free-fall / inertial wake up acceleration threshold msb fwd7 fwd6 fwd5 fwd4 fwd3 fwd2 fwd1 fwd0 fwd7, fwd0 minimum duration of the free-fall/wake-up event duration s () ff_wu_duration (dec) odr ----------------------------------------------------------- =
LIS3LV02DL register description 31/36 7.25 dd_cfg (38h) direction-detector configuration register iend lir zhie zlie yhie ylie xhie xlie iend interrupt enable on direction change. default value: 0 (0: disabled; 1: interrupt signal enabled) lir latch interrupt request into dd_src reg with the dd_src reg cleared by reading dd_ack reg. default value: 0. (0: interrupt request not latched; 1: interrupt request latched) zhie enable interrupt generation on z high event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured acce l. value higher than preset threshold) zlie enable interrupt generation on z low event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured acce l. value lower than preset threshold) yhie enable interrupt generation on y high event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured acce l. value higher than preset threshold) ylie enable interrupt generation on y low event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured acce l. value lower than preset threshold) xhie enable interrupt generation on x high event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured acce l. value higher than preset threshold) xlie enable interrupt generation on x low event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured acce l. value lower than preset threshold)
register description LIS3LV02DL 32/36 7.26 dd_src (39h) direction detector source register 7.27 dd_ack (3ah) dummy register. if lir bit in dd_cfg=1 allows the refresh of dd_src. read data is not significant. x ia zhzlyhylxhxl ia interrupt event from direction change. (0: no direction changes detected; 1: direction has changed from previous measurement) zh z high. default value: 0 (0: z below thsi threshold; 1: z accel. exceeding thse threshold along positive direction of acceleration axis) zl z low. default value: 0 (0: z below thsi threshold; 1: z accel. exceeding thse threshold along negative direction of acceleration axis) yh y high. default value: 0 (0: y below thsi threshold; 1: y accel. exceeding thse threshold along positive direction of acceleration axis) yl y low. default value: 0 (0: y below thsi threshold; 1: y accel. exceeding thse threshold along negative direction of acceleration axis) xh x high. default value: 0 (0: x below thsi threshold; 1: x accel. exceeding thse threshold along positive direction of acceleration axis) xl x low. default value: 0 (0: x below thsi threshold; 1: x accel. exceeding thse threshold along negative direction of acceleration axis)
LIS3LV02DL register description 33/36 7.28 dd_thsi_l (3ch) 7.29 dd_thsi_h (3dh) 7.30 dd_thse_l (3eh) 7.31 dd_thse_h (3fh) thsi7 thsi6 thsi5 thsi4 thsi3 thsi2 thsi1 thsi0 thsi7, thsi0 direction detection internal threshold lsb thsi15 thsi14 thsi13 thsi12 thsi11 thsi10 thsi9 thsi8 thsi15, thsi8 direction detection internal threshold msb thse7 thse6 thse5 thse4 thse3 thse2 thse1 thse0 thse7, thse0 direction detection external threshold lsb thse15 thse14 thse13 thse1 2 thse11 thse10 thse9 thse8 thse15, thse8 direction detection external threshold msb
package information LIS3LV02DL 34/36 8 package information in order to meet environmental requirements, st offers these devices in ecopack ? packages. these packages have a lead-free second level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com. figure 10. lga-16 mechanical data & package dimensions outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a1 0.92 1 0.0394 a2 0.7 0.0276 a3 0.180 0.220 0.260 0.0071 0.0087 0.0102 d1 4.250 4.400 4.550 0.1673 0.1732 0.1791 e1 7.350 7.500 7.650 0.2894 0.2953 0.3012 e 1.0 0.0394 d 0.3 0.0118 l1 5.000 0.1969 n 2.5 0.0984 n1 1.2 0.0472 p1 0.965 0.975 0.985 0.0380 0.0384 0.0388 p2 0.64 0.65 0.66 0.0252 0.0256 0.0260 t1 0.75 0.8 0.85 0.0295 0.0315 0.0335 t2 0.45 0.5 0.55 0.0177 0.0197 0.0217 r 1.200 1.600 0.0472 0.0630 h 0.150 0.0059 k 0.050 0.0020 i 0.100 0.0039 s 0.100 0.0039 lga16 (4.4x7.5x1mm) l and g rid a rray package 7863679 b e1 p2 l1 t2 d1 p1 b a c i a3 r a2 a1 12 4 5 6 7 8 16 15 9 10 11 12 13 14 3 n1 e t1 s e n d detail a detail a metal pad seating plane solder mask opening i e c d d a e b i b a c h d k b a c h b a c i e k k (4 x)
LIS3LV02DL revision history 35/36 9 revision history table 8. document revision history date revision changes 15-feb-2006 1 initial release.
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